Recently, a multicarrier transmission system is a center of attention as a transmission system of digital signals. The multicarrier transmission system is a modulation system of serial/parallel-converting data to be transmitted to lower the symbol rate and then assigning data to an amplitude and a phase of a plurality of sub bands which are orthogonal to each other, so as to transmit the data. The multicarrier transmission system divides a transmission band into a plurality of sub bands for transmitting data. Accordingly, the multicarrier transmission system can vary the modulation system for each sub band, and therefore can flexibly use the frequency. The multicarrier transmission system also lowers the symbol rate, and therefore increases the resistance against the delay wave. For these reasons, the multicarrier transmission system is strong against multipath disturbance.
As a multicarrier transmission system, OFDM (orthogonal frequency division multiplexing), wavelet modulation using an orthogonal wavelet function, and the like have been proposed.
FIG. 10 shows a structure of a conventional OFDM reception device 210 disclosed in patent document 1. As shown in FIG. 10, the OFDM reception device 210 includes an A/D converter 201, a clock generation circuit 202, a complex multiplication circuit 203, a guard correlation calculation circuit 204, a numerical controlled oscillator (NCO) 205, a fast Fourier transform circuit 206, a carrier frequency error calculation circuit 207, a clock frequency reproduction circuit 208, and a data demodulation unit 209.
The A/D converter 201 samples a received signal and converts the received signal into a digital signal, based on a clock which is input from the clock generation circuit 202.
The complex multiplication circuit 203 multiples a complex sine wave signal which is input from the NCO 205 by the received signal converted into the digital signal, and corrects a frequency error.
The frequency error is first roughly estimated by the guard correlation calculation circuit 204. In order to increase the resistance against the delay wave, an OFDM signal includes a guard interval cyclically repeated in an OFDM symbol. The guard correlation calculation circuit 204 calculates a correlation value between an input OFDM signal and an OFDM signal delayed by an effective symbol time. The guard correlation calculation circuit 204 obtains a timing at which the correlation is peaked and a phase of the OFDM signal at that timing. Based on the obtained phase, the guard correlation calculation circuit 204 obtains a phase difference at an effective symbol time interval. The phase difference corresponds to the frequency error. Accordingly, the guard correlation calculation circuit 204 controls the NCO 205 so as to counteract the frequency error.
The timing at which the correlation is peaked represents an effective symbol interval. Based on the timing, the fast Fourier transform circuit 206 transforms an OFDM signal, having a rough frequency thereof corrected, into a signal in the frequency range, and outputs an amplitude and a phase of each of sub bands. The data demodulation unit 209 demodulates data of each sub band based on such an amplitude and phase.
An OFDM signal has a pilot signal, assigned a predetermined phase and amplitude, inserted into a predetermined sub band. In a conventional OFDM reception device, frequency error correction, equalization and the like are performed based on such a pilot signal.
The carrier frequency error calculation circuit 207 extracts only a predetermined pilot signal based on information on each sub band which is output from the fast Fourier transform circuit 206. The carrier frequency error calculation circuit 207 estimates a residual frequency error based on a phase change of the predetermined pilot signal. The carrier frequency error calculation circuit 207 controls the NCO 205 based on the residual frequency error. Thus, more precise carrier frequency synchronization is performed.
The clock frequency reproduction circuit 208 estimates a clock frequency error based on the phase change of the pilot signal. The clock frequency reproduction circuit 208 controls the clock generation circuit 202 based on the clock frequency error. Thus, the clock frequency error is corrected.
Patent Document 1: Japanese Laid-Open Patent Publication No. 10-308715